I. Field of the Invention
The present invention relates to the field of semiconductor devices. More specifically, the present invention relates to the field of fabrication of semiconductor devices.
II. Background Information
Modern day Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFET) utilize gates made of polysilicon gates. One disadvantage in utilizing polysilicon gates for MOSFETs is the depletion effect that affects polysilicon gates. At inversion, a polysilicon gate generally experiences depletion of carriers in the area of the polysilicon adjacent the gate dielectric. The depletion effect reduces the effective gate capacitance of the MOSFET incorporating a polysilicon gate. Ideally, it is desirable that the gate capacitance is high. The higher the gate capacitance, more charge is accumulated on both sides of the gate capacitor, and therefore more charge is accumulated in the channel. As more charge is accumulated in the channel, the drain-source current becomes higher when the transistor is biased.
FIG. 1 illustrates in simplified form a cross-sectional view through a MOSFET that has a polysilicon gate 8. Due to the polysilicon material of gate 8, the depletion effect causes charged carriers to accumulate near interface 12 between gate 8 and the gate oxide dielectric 2. Accordingly, the effective gate capacitance, theoretically expressed by the formula C=xcex5/T decreases (xcex5 is the dielectric constant of gate oxide 2 and T is the distance between the plates of the capacitor). This is due to an xe2x80x9cincreasexe2x80x9d in the effective distance between the charges accumulated on both sides of the gate oxide 2. The effective distance that separates the charge on both sides of gate oxide 2 becomes approximately X instead of T. The distance X is larger than T due to the depletion of charge, in the polysilicon gate 8, in the vicinity of interface 12. Accordingly, polysilicon gate 8 causes the effective gate capacitance to decrease.
FIG. 2 illustrates a cross-sectional view through a MOSFET 14 with a silicided polysilicon gate 16. The polysilicon gate 16 has a layer of silicide 18 formed on top thereof. The layer of silicide 18 contributes to a decrease in the resistance R of the polysilicon gate 16. The decrease in resistance R causes a decrease in the time propagation delay RC of gate 16. While silicide 18 may help decrease the resistance of the gate, charge is still depleted in the vicinity of interface 20 between gate 16 and gate oxide 117, thereby causing a smaller effective gate capacitance.
FIG. 3 illustrates a cross-sectional view through a MOSFET transistor with a gate electrode 22 made entirely of metal. The metal of gate 22 helps prevent depletion of charge through the gate 22. This prevents the effective thickness of the gate capacitor to increase and the capacitance to decrease as a result of the depletion effect. However, utilization of gate electrodes built entirely of metal poses problems in the case of PMOS and NMOS pairs of devices built according to the complementary metal oxide semiconductor (CMOS) technology.
FIG. 4 illustrates a pair of NMOS 28 and PMOS 29 devices. The PMOS and NMOS devices 28 and 29 respectively have different Fermi levels. A semiconductor, such as silicon, for example, has a certain energy level conventionally measured by its Fermi level. The intrinsic Fermi level of an undoped semiconductor is typically at the middle of the bandgap, between conduction and valence band edges. In an N-type doped silicon the Fermi level is closer to the conduction band while in a P-type doped silicon the Fermi level is closer to the valence band.
Metal gate electrodes have been used, in NMOS and PMOS devices built according to CMOS technology, in the form of mid-bandgap metal gate electrodes. These metal gate electrodes have a Fermi level selected midway between the Fermi level of NMOS and PMOS devices to maintain symmetry between NMOS and PMOS devices (mid-bandgap metal technique). The shortcoming of the mid-bandgap metal technique is that a mid-bandgap metal cannot deliver the small threshold voltage (Vt) necessary for future technologies without degrading short channel effects.
It is desirable to provide a pair of NMOS and PMOS transistors and a process for fabricating these transistors where the gate depletion effect is reduced, if not eliminated, and both the NMOS and PMOS transistors operate at Fermi levels at which both the NMOS and the PMOS devices perform optimally.
The present invention provides a method of forming first and second transistor devices. A first region of silicide is formed over a first portion of a gate dielectric that overlies a first well region in a semiconductor substrate. A second region of silicide is formed over a second portion of the gate dielectric. The second portion of the gate dielectric overlies a second well region in the semiconductor substrate. First and second doped junction regions are formed in the first and second well regions respectively.